DRAM (dynamic random-access memory) is a type of volatile semiconductor memory that stores each bit as electric charge in a tiny capacitor paired with a single access transistor. It is called dynamic because that charge leaks away within milliseconds, so the memory must be refreshed continuously. In computer hardware, DRAM is the technology behind main memory: DDR4 and DDR5 modules, LPDDR in phones and laptops, GDDR on graphics cards and HBM in accelerators.
DRAM dominates memory because its one-transistor, one-capacitor cell is extremely small, which makes high capacity affordable. The price is higher latency and power overhead than SRAM, the faster but much larger memory used for processor caches.
How a DRAM cell stores and loses data
Each DRAM cell consists of an access transistor and a storage capacitor. A charged capacitor represents one logical value and a discharged capacitor the other. Cells are arranged in a grid: the wordline selects a row by switching on its transistors, and each column connects to a bitline that carries the tiny charge to a sense amplifier.
Reading is destructive. When a row is opened, every capacitor in it shares its charge with its bitline, and the sense amplifiers detect a very small voltage difference and amplify it to a full logic level. The amplified values are then written back into the cells, which is why opening a row also restores it.
Because capacitors leak, every row must be refreshed within a retention window of 64 ms at normal temperature under JEDEC standards, and typically 32 ms above about 85 °C. The memory controller issues refresh commands at regular intervals, and during a refresh the affected banks cannot serve requests, which costs bandwidth and energy.
How DRAM is organized and accessed
A DRAM chip is divided into a hierarchy that lets several operations overlap. Understanding it explains why access patterns affect performance so strongly.
| Level | Description | Why it matters |
|---|---|---|
| Channel | Independent data path from the memory controller | More channels add bandwidth |
| Rank | Set of chips that respond together | Ranks can interleave to hide delays |
| Bank group and bank | Independent arrays inside a chip | Different banks can work in parallel |
| Row | Page of a few kilobytes opened at once | Hits in an open row are fast |
| Column | Location within the open row | Selected by the read or write command |
An access follows a fixed sequence. The controller sends an activate command to open a row, waits, issues a read or write to a column, and later sends a precharge to close the row. Each step has a timing parameter, and these parameters together determine memory latency.
| Parameter | Meaning | Typical absolute value |
|---|---|---|
| CL (CAS latency) | Read command to first data | About 10 to 16 ns |
| tRCD | Row activate to column command | About 10 to 16 ns |
| tRP | Precharge to next activate | About 10 to 16 ns |
| tRAS | Minimum time a row stays open | About 30 to 40 ns |
| tRFC | Duration of one refresh | Hundreds of nanoseconds, growing with density |
Timings are usually quoted in clock cycles, so a higher cycle count at a higher frequency can represent the same absolute delay. Comparing modules requires converting to nanoseconds rather than reading CL numbers alone.
Types of DRAM
All modern variants share the same cell principle but differ in interface, voltage and packaging, each optimized for a different balance of bandwidth, capacity and power.
| Family | Typical use | Main optimization | Typical form |
|---|---|---|---|
| DDR4 | Desktops, servers, older laptops | Capacity and cost | DIMM and SO-DIMM, 1.2 V |
| DDR5 | Current desktops and servers | Bandwidth and density | DIMM with on-module power management, 1.1 V |
| LPDDR5 and LPDDR5X | Phones, thin laptops | Low power | Soldered or CAMM2 modules |
| GDDR6 and GDDR7 | Graphics cards | Very high bandwidth per pin | Soldered around the GPU |
| HBM | AI accelerators, data center GPUs | Extreme bandwidth per watt | 3D stacks on an interposer |
DDR5 introduced two independent 32-bit subchannels per module, longer bursts and on-die ECC that corrects internal cell errors. On-die ECC improves chip reliability but is not the same as system-level ECC, which protects data on its way to the processor.
DRAM compared with SRAM and flash
DRAM occupies the middle of the memory hierarchy, between fast on-chip SRAM and slow, non-volatile flash storage.
| Property | SRAM | DRAM | NAND flash |
|---|---|---|---|
| Cell structure | Six transistors | One transistor, one capacitor | Floating gate or charge trap |
| Volatility | Volatile | Volatile, needs refresh | Non-volatile |
| Access latency | About 1 to 10 ns | About 50 to 100 ns load-to-use | Tens of microseconds |
| Density and cost per bit | Low density, high cost | High density, moderate cost | Highest density, lowest cost |
| Typical role | CPU caches | Main memory | SSD storage |
Limitations and reliability concerns
DRAM scaling has become difficult. Shrinking cells leaves capacitors with less charge, which makes them more sensitive to leakage and interference. The best-known consequence is Rowhammer: repeatedly activating one row can flip bits in neighboring rows. Mitigations include target row refresh and refresh management in DDR5, but they do not eliminate the risk entirely.
- Refresh overhead grows as chips gain capacity, taking a larger share of time and power.
- Soft errors from radiation or electrical noise can flip bits, which is why servers use ECC.
- Data remanence means contents can persist briefly after power loss, especially when cold.
- Latency improves slowly: absolute access time has changed little across generations while bandwidth has grown.
The simple explanation
DRAM is the computer’s short-term working memory. Each bit of information is stored as a tiny amount of electricity in a microscopic bucket. The buckets leak, so the computer tops them up thousands of times per second to keep the data intact.
This design lets manufacturers pack billions of buckets onto a small chip at a reasonable price. When the power is turned off, the buckets empty and everything in DRAM is lost, which is why files must be saved to storage.
How it is used in practice
A small engineering firm runs simulations on a workstation with 32 GB of dual-channel DDR4. Large models exceed that capacity, so the operating system pages data to the SSD and runs that should take one hour take most of a day.
The firm moves to a new workstation with 128 GB of DDR5 ECC memory across four channels. The full model now fits in memory, ECC protects week-long runs from silent bit errors, and the higher bandwidth keeps all processor cores supplied with data.
Typical simulation runs return to about one hour, and the engineers can test several design variants in a single working day instead of one.