Memory bandwidth is the maximum rate at which data can be transferred between memory and a processor, usually expressed in gigabytes per second (GB/s). In computer memory, it describes how much data per second a CPU, GPU or accelerator can read from or write to its RAM, and it is one of the two fundamental memory performance metrics alongside memory latency.
Bandwidth is primarily a property of the memory interface: the transfer rate of each data line, the width of the bus and the number of channels. It decides how fast a processor can be fed with data, which makes it the limiting factor for many graphics, AI, scientific and integrated GPU workloads.
How memory bandwidth is calculated
Theoretical peak bandwidth follows a simple formula: transfer rate multiplied by bus width in bytes, multiplied by the number of channels. The transfer rate is given in megatransfers per second (MT/s), often loosely written as MHz on retail packaging. Because DDR memory transfers data on both clock edges, a DDR5-6000 module runs at an I/O clock of 3,000 MHz but performs 6,000 million transfers per second.
A standard DIMM provides a 64-bit data path, which equals 8 bytes per transfer. DDR5-6000 therefore delivers 6,000 × 8 = 48 GB/s per channel, and a typical dual-channel desktop reaches about 96 GB/s. DDR5 splits each DIMM into two independent 32-bit subchannels, which improves efficiency but does not change the total bus width. The table below shows typical peak values for common configurations.
| Configuration | Transfer rate | Total bus width | Peak bandwidth |
|---|---|---|---|
| DDR4-3200, dual channel | 3,200 MT/s | 128 bits | About 51 GB/s |
| DDR5-6000, dual channel | 6,000 MT/s | 128 bits | About 96 GB/s |
| LPDDR5X-8533, 128-bit | 8,533 MT/s | 128 bits | About 137 GB/s |
| DDR5-4800, 12 channels (server) | 4,800 MT/s | 768 bits | About 461 GB/s |
| GDDR7 at 28 Gbps, 256-bit | 28 Gbps per pin | 256 bits | About 896 GB/s |
| HBM3, one stack | 6.4 Gbps per pin | 1,024 bits | About 819 GB/s |
Peak versus sustained bandwidth
The calculated figure is a theoretical ceiling that real programs never fully reach. Refresh cycles, bank conflicts, read-write turnarounds, page misses and controller scheduling all consume time on the bus. Well-optimized streaming code on a CPU commonly achieves somewhere around 70 to 90 percent of peak, while random access patterns achieve far less.
Sustained bandwidth is usually measured with streaming benchmarks such as STREAM, which run copy, scale, add and triad loops over arrays much larger than the caches. A single CPU core often cannot saturate the memory system by itself, because it can keep only a limited number of cache misses in flight; several cores together are needed to reach the platform maximum.
| Factor | Effect | Mitigation |
|---|---|---|
| Random access patterns | Many partial cache lines and page misses | Restructure data for sequential access |
| Single-channel installation | Halves the available bus width | Populate channels in matched pairs |
| Mixed read and write traffic | Bus turnaround penalties | Batch reads and writes |
| Too few outstanding requests | Latency dominates throughput | Use more threads or prefetching |
| Shared integrated GPU | CPU and GPU compete for one memory pool | Faster memory, dedicated VRAM |
Memory bandwidth compared with latency and capacity
Bandwidth, latency and capacity are independent properties that are often confused. Bandwidth measures throughput, latency measures the delay for a single access, and capacity measures how much data fits. A memory upgrade can improve one while worsening another, for example when a faster DDR5 kit carries higher CAS latency in cycles.
| Metric | Unit | What it limits | Workloads most affected |
|---|---|---|---|
| Memory bandwidth | GB/s | Volume of data per second | Graphics, AI inference, simulation |
| Memory latency | Nanoseconds | Delay of each dependent access | Games, databases, pointer-heavy code |
| Memory capacity | GB | Size of the working set | Virtual machines, large datasets |
Different memory types make different trade-offs. HBM stacks dies next to the processor with a very wide bus for extreme bandwidth, GDDR runs very fast narrow pins for graphics cards, and LPDDR soldered close to the processor favors efficiency. Modules such as DIMM, SO-DIMM and CAMM2 define the physical form, while channel count largely sets the bandwidth on a platform.
When memory bandwidth becomes the bottleneck
A workload is bandwidth-bound when its processor waits for data rather than for arithmetic. The roofline model expresses this with arithmetic intensity, the number of operations performed per byte loaded. Code with low intensity, such as vector addition or large language model token generation, is limited by bandwidth, while dense matrix multiplication with good reuse is limited by compute.
- Integrated graphics depend on system RAM, so moving from single to dual channel can raise frame rates dramatically.
- Local AI inference on large models generates each token by reading most of the weights, so token speed roughly scales with available bandwidth divided by model size.
- Scientific computing on servers benefits from more memory channels per socket rather than higher core counts alone.
- Video editing with high-resolution footage moves large frames continuously and gains from both bandwidth and capacity.
Common mistakes and misconceptions
The most common error is installing a single module in a dual-channel system, which halves peak bandwidth regardless of the module’s speed. Another is assuming that an enabled XMP or EXPO profile guarantees the rated speed; stability depends on the memory controller and the motherboard, especially with four modules.
It is also misleading to compare GPU and CPU bandwidth figures directly. A graphics card’s VRAM bandwidth serves only the GPU, whereas system memory bandwidth is shared by all CPU cores and any integrated graphics. Finally, a high bandwidth number does not compensate for insufficient capacity: once data spills to storage, performance drops by orders of magnitude.
In everyday language
Memory bandwidth is like the number of lanes on a highway between a warehouse and a factory. The factory, which is the processor, can work only as fast as trucks deliver materials. More lanes and faster trucks mean more material per second.
If the factory is very fast but the road is narrow, machines stand idle waiting for deliveries. That is why two memory sticks in matching slots, which open a second set of lanes, can make a noticeable difference in some tasks. Bandwidth is about volume, not about how long a single trip takes.
Seen in the real world
A student buys a budget laptop with integrated graphics and a single 16 GB DDR5-5600 module. Games run at low frame rates, and a local language model generates text slowly. A diagnostic tool shows that memory is running in single-channel mode with about 45 GB/s of peak bandwidth.
The student replaces the module with a matched kit of two 8 GB modules at the same speed. Capacity stays at 16 GB, but the system now runs in dual-channel mode at about 90 GB/s. Frame rates in the same games rise substantially, and the language model produces tokens noticeably faster, because both workloads were limited by how quickly data could be read from memory rather than by processor speed.