SRAM (static random-access memory) is a type of volatile semiconductor memory that stores each bit in a bistable latch of transistors, usually six per bit, so the data stays stable without periodic refresh as long as power is applied. It offers the lowest latency of any mainstream memory, which is why it forms CPU and GPU caches, register files and on-chip buffers.
In computer memory hardware, SRAM sits at the top of the memory hierarchy, above DRAM. The price of its speed is low density and high cost per bit: an SRAM cell occupies many times the area of a DRAM cell, so systems contain megabytes of SRAM but gigabytes of DRAM.
How an SRAM cell stores a bit
The standard 6T SRAM cell consists of two cross-coupled inverters that form a latch and two access transistors that connect the latch to a pair of complementary bit lines. One inverter output holds the bit, the other holds its inverse, and positive feedback keeps the state stable indefinitely while the supply voltage is present.
To read, the word line opens the access transistors, the precharged bit lines start to separate by a small voltage, and a sense amplifier detects the difference within a fraction of a nanosecond. To write, drivers force the bit lines to the new values strongly enough to flip the latch. Transistor sizing must balance read stability against writability, which becomes harder as voltages drop.
Because the latch actively holds its state, SRAM has no refresh cycle, unlike DRAM, whose capacitors leak charge and must be refreshed roughly every 64 milliseconds. SRAM still draws leakage current through its transistors, which is a major share of standby power in large caches.
Cells are arranged in arrays of rows and columns, with row decoders driving word lines and column multiplexers selecting bit lines. A large cache is split into many small subarrays or banks, because long bit lines add capacitance and slow down sensing. Splitting also allows several accesses to proceed in parallel.
SRAM compared with DRAM and other memories
SRAM and DRAM are complementary rather than competing technologies. The table summarizes the trade-offs that determine where each one is used.
| Property | SRAM | DRAM | NAND flash |
|---|---|---|---|
| Storage element | Six-transistor latch | One transistor and one capacitor | Floating gate or charge trap |
| Volatility | Volatile | Volatile | Non-volatile |
| Refresh needed | No | Yes, about every 64 ms | No |
| Typical access time | Below 1 ns to a few ns | Tens of ns | Tens of microseconds |
| Density and cost | Low density, high cost per bit | High density, moderate cost | Highest density, lowest cost |
| Main use | Caches, registers, buffers | Main memory, VRAM | Storage |
Technologies such as HBM and DDR5 improve DRAM bandwidth, but they cannot match the single-cycle access of SRAM placed directly next to the execution units. Conversely, no practical system could afford gigabytes of SRAM for main memory.
Where SRAM is used
Almost all SRAM today is embedded on the same die as the logic it serves. Discrete SRAM chips still exist for networking equipment, industrial controllers and some microcontroller systems, but they are a niche.
| Level | Typical size | Typical latency | Purpose |
|---|---|---|---|
| Register file | Hundreds of bytes to a few KB per core | Within one cycle | Operands for current instructions |
| L1 cache | 32 to 64 KB per core, per type | About 4 to 5 cycles | Hottest code and data |
| L2 cache | 512 KB to 3 MB per core | About 12 to 20 cycles | Working set of a core |
| L3 or last-level cache | Several MB to over 100 MB | About 40 to 70 cycles | Shared data between cores |
| Accelerator scratchpad | Tens to hundreds of MB | Few cycles | AI weights and activations |
Exact figures vary by processor design and clock speed. Stacked cache technologies place additional SRAM dies on top of the processor, enlarging the last-level cache without enlarging the main die, which benefits latency-sensitive workloads such as games.
Variants and design parameters
Designers choose among several cell types and organizations depending on speed, area and operating voltage.
| Variant | Characteristic | Typical use |
|---|---|---|
| 6T cell | Smallest standard cell | General caches |
| 8T cell | Separate read port, stable at low voltage | Low-power and register files |
| Dual-port SRAM | Two simultaneous accesses | FIFOs, video and network buffers |
| Asynchronous SRAM | No clock, simple interface | Discrete chips in embedded systems |
| Pseudo-SRAM | DRAM core with SRAM-like interface | Low-cost embedded memory |
Key parameters include the bit cell area, the minimum operating voltage (Vmin), access time, leakage and soft error rate. Large caches protect data with parity or ECC, because cosmic radiation and alpha particles can flip stored bits.
Scaling limits and misconceptions
SRAM density has scaled much more slowly than logic in recent process nodes. Moving from about 5 nm to 3 nm class processes brought only a small reduction in bit cell area, while logic density improved more. As a result, cache can occupy a large fraction of a modern processor die, and chip designers increasingly move cache to separate, cheaper dies through chiplet packaging.
- SRAM is not non-volatile: static means no refresh is needed, not that data survives power loss.
- More cache is not always faster: larger caches have higher latency, so hierarchy design is a balance.
- SRAM is not used for main memory in PCs, because its cost per bit is far too high.
Lowering the supply voltage saves power but shrinks the noise margin of each cell. Below a certain voltage, a small fraction of cells fails to read or write reliably, so low-power designs use assist circuits, 8T cells or a separate, higher cache voltage rail to keep caches stable while the logic runs at lower voltage.
A plain-language summary
SRAM is the fastest memory in a computer, built right into the processor. Each bit is held by a tiny switch circuit that stays in place by itself, like a light switch that remains on until someone flips it. The main memory works differently. It is more like a bucket that slowly leaks and must be refilled many times per second.
Because SRAM is fast but bulky and expensive, a computer uses only a small amount of it for the data it needs right now.
An example from practice
A game studio profiles its open-world game on two desktop processors with the same core count and similar clock speeds. One has a 32 MB last-level cache, the other has a 96 MB cache made larger with stacked SRAM.
In crowded city scenes, the simulation code repeatedly walks large arrays of character and physics data. On the smaller cache, many of these accesses miss and wait for DRAM, costing around a hundred nanoseconds each. On the larger cache, most of the working set stays in SRAM, and the measured average frame rate rises by about 15 percent, with fewer stutters. The studio then reorganizes its data layout to be more compact, which helps both processors by keeping more data inside the cache.