PCIe, short for PCI Express, is the high-speed serial point-to-point interface that connects expansion cards, NVMe storage and onboard controllers to the processor and chipset of a computer. On motherboards, PCIe defines both the physical slots and M.2 sockets that devices plug into and the lane wiring that decides how much bandwidth each device actually receives.
In hardware design, PCIe replaced the older shared parallel buses (PCI and AGP) in the mid-2000s. Each device gets a dedicated link made of one or more lanes, so devices no longer compete for a single shared bus, and bandwidth scales with both the lane count and the generation of the link.
How a PCIe link moves data
A PCIe link is built from lanes, and each lane consists of two differential pairs: one pair transmits and one pair receives, so every lane works in full duplex. A link may combine 1, 2, 4, 8 or 16 lanes, written as x1, x2, x4, x8 and x16, and data is striped across all lanes of the link in parallel.
The protocol is organized in three layers. The transaction layer builds packets called TLPs that carry memory reads, writes and interrupts. The data link layer adds sequence numbers and a CRC and retransmits any packet the receiver rejects, which makes the link reliable without help from software. The physical layer handles encoding, clock recovery and the electrical signaling.
The topology is a tree. The root complex, which in modern systems lives inside the CPU, sits at the top; switches fan one upstream link out to several downstream links; endpoints such as graphics cards and SSDs sit at the leaves. The chipset itself is attached to the CPU through a link that is electrically very close to PCIe, which is why devices behind the chipset share that single uplink.
When a device powers up, both ends run link training, a negotiation that settles the highest generation and widest lane count both sides and the board wiring support. A link therefore always runs at the lowest common denominator: a Gen 4 card in a Gen 3 slot runs at Gen 3, and an x16 card in a slot wired for four lanes runs at x4.
PCIe generations and bandwidth
Each PCIe generation has roughly doubled the transfer rate per lane while keeping backward compatibility. The figures below are approximate usable bandwidth per lane in one direction, after encoding overhead; total link bandwidth is the per-lane figure multiplied by the lane count.
| Generation | Transfer rate | Encoding | Approx. per lane | Approx. x16 link |
|---|---|---|---|---|
| PCIe 1.0 | 2.5 GT/s | 8b/10b | 250 MB/s | 4 GB/s |
| PCIe 2.0 | 5 GT/s | 8b/10b | 500 MB/s | 8 GB/s |
| PCIe 3.0 | 8 GT/s | 128b/130b | 985 MB/s | 15.8 GB/s |
| PCIe 4.0 | 16 GT/s | 128b/130b | 1.97 GB/s | 31.5 GB/s |
| PCIe 5.0 | 32 GT/s | 128b/130b | 3.94 GB/s | 63 GB/s |
| PCIe 6.0 | 64 GT/s | PAM4 with FLIT and FEC | About 7.5 GB/s | About 121 GB/s |
The move from 8b/10b to 128b/130b encoding in PCIe 3.0 cut the overhead from 20 percent to about 1.5 percent. PCIe 6.0 changed the signaling itself to PAM4, which carries two bits per symbol, and added forward error correction with fixed-size flow control units because PAM4 is more sensitive to noise. Consumer motherboards currently top out at PCIe 5.0, while 6.0 appears first in servers and data centers.
Slots, lanes and lane allocation on the motherboard
The most important practical fact is that slot size and electrical width are separate. A full-length x16 slot may be wired with only four or eight lanes, and board specifications describe this as an x16 (x4 electrical) slot. The mechanical size only guarantees that a card fits.
Lanes come from two pools. The CPU lanes connect directly to the processor and usually feed the primary graphics slot and one or two M.2 sockets. The chipset lanes feed the remaining slots, extra M.2 sockets, USB and network controllers, and they all share the chipset uplink, so heavy simultaneous traffic behind the chipset can saturate it.
| Link width | Typical devices | Notes |
|---|---|---|
| x1 | Network cards, sound cards, USB controllers | Short slot; enough for most single-function cards |
| x4 | NVMe SSDs, 10-gigabit network cards, capture cards | Standard width for M.2 NVMe sockets |
| x8 | Server adapters, RAID controllers, second GPU | Often produced by splitting an x16 slot |
| x16 | Graphics cards, accelerators | Primary slot, normally wired to the CPU |
Boards often share lanes between connectors. Populating a second M.2 socket may drop the main graphics slot from x16 to x8, or disable two SATA ports. Bifurcation is the related firmware feature that splits one x16 slot into x8/x8 or x4/x4/x4/x4, which is required for passive adapters that hold four NVMe drives in one slot.
PCIe compared with related interfaces
PCIe is the transport underneath several other names, which causes frequent confusion. M.2 is a connector and form factor, NVMe is a storage protocol running over PCIe, and Thunderbolt and USB4 tunnel PCIe traffic over a cable.
| Interface | What it is | Relation to PCIe |
|---|---|---|
| Conventional PCI | Shared parallel bus, 133 MB/s | Predecessor; replaced by PCIe |
| M.2 slot | Small connector for SSDs and wireless cards | Carries PCIe x4, SATA or both |
| NVMe | Storage command protocol | Runs on top of PCIe lanes |
| SATA | Storage interface, 6 Gb/s | Separate, much slower link |
| Thunderbolt and USB4 | External cable interfaces | Tunnel PCIe for external devices |
| CXL | Cache-coherent interconnect | Reuses the PCIe physical layer |
The difference from SATA matters for storage choices: an M.2 SSD in SATA mode is limited to about 550 MB/s, while the same socket in PCIe 4.0 x4 mode allows roughly 7 GB/s. Checking which mode a given M.2 socket supports avoids buying a drive the board cannot run.
Power, compatibility and configuration
A PCIe slot supplies power as well as data. An x16 graphics slot delivers up to 75 W, and higher-power cards add auxiliary connectors: a 6-pin connector adds 75 W, an 8-pin connector adds 150 W, and the 12V-2×6 connector used by current high-end cards is rated for up to 600 W.
Firmware settings influence how links behave. The link speed setting can force a lower generation when a riser cable or long trace causes errors. Resizable BAR lets the CPU map the full graphics memory at once instead of 256 MB windows. ASPM (Active State Power Management) lowers link power in idle periods, which saves energy in laptops but occasionally causes instability with specific cards.
Higher generations are harder to route. PCIe 5.0 signals lose strength quickly over copper, so boards and long risers often need retimers or redrivers to restore the signal, and cheap riser cables are a common source of link errors and downtraining.
Common mistakes and misconceptions
Most PCIe problems on desktop systems come from mismatched expectations about lane wiring rather than from faulty hardware. The table maps frequent symptoms to their causes.
| Symptom | Likely cause | Fix |
|---|---|---|
| Graphics card runs at x8 | Lanes shared with a populated M.2 socket | Move the SSD to a chipset-attached socket |
| SSD slower than rated | Socket runs an older generation or fewer lanes | Use a CPU-attached Gen 4 or Gen 5 socket |
| Card not detected | Slot disabled by lane sharing or bifurcation | Check the board manual and firmware settings |
| Random crashes at Gen 5 | Signal loss through a riser or long trace | Force Gen 4 or use a certified riser |
A frequent misconception is that a newer generation always brings visible gains. A graphics card loses only a small share of performance when it drops one generation or from x16 to x8, while NVMe storage and multi-GPU compute workloads are far more sensitive to link bandwidth.
The idea in brief
PCIe is the set of high-speed roads inside a computer that connect the processor to the graphics card, the fast storage drives and other add-on parts. Each road has a number of lanes, and more lanes and a newer generation mean more traffic can pass at once.
The slot you see on the motherboard is only the entrance. What matters is how many lanes are actually wired behind it and whether it connects straight to the processor or through the chipset, which is a shared side road.
A practical scenario
A video editor builds a workstation with one graphics card and three NVMe SSDs on a desktop board whose processor provides 24 usable PCIe lanes. The plan is a Gen 4 graphics card in the main x16 slot, the project drive and one archive drive in the two CPU-attached M.2 sockets, and the second archive drive in a chipset socket.
After installation, a diagnostic tool shows the graphics card running at x8 instead of x16. The board manual explains that the second CPU-attached M.2 socket borrows eight lanes from the main slot. The editor moves one archive drive to a chipset socket, the card returns to x16 at Gen 4, and the project drive keeps its direct CPU link with sustained reads of about 7 GB/s, so timeline scrubbing with 8K footage stays smooth.