A chiplet is a small, functionally specialized silicon die designed to be combined with other dies inside one package so that together they behave as a single chip. In semiconductors within hardware, the chiplet approach replaces one large monolithic die with several smaller ones, for example compute dies, an I/O die and memory dies, connected by high-density die-to-die interconnects.
Chiplets matter because yield, cost and reticle limits make very large monolithic dies increasingly impractical at advanced process nodes. Splitting a design lets each part be built on the process best suited to its function and lets manufacturers reuse the same dies across many products.
Why chiplets improve yield and cost
Every wafer contains random defects, and a single defect can ruin the die it lands on. The probability that a die is defect-free falls roughly exponentially with its area, so a die twice as large is much more than twice as likely to fail. Smaller chiplets therefore produce a higher share of good dies per wafer.
A second limit is the reticle size of photolithography scanners, roughly 26 by 33 mm, which caps the area of a single die. Chiplets allow products far larger than one reticle without stitching. A third benefit is heterogeneous integration: analog and I/O circuits, which barely shrink at new nodes, can stay on a mature, cheaper process while logic moves to the newest one.
Chiplets also enable known good die (KGD) testing. Each die is tested before assembly, so a defect discards one small part instead of an entire large chip, and binning can mix dies of different quality grades into different product tiers.
Packaging and interconnect technologies
Chiplets only work if the dies can communicate almost as efficiently as circuits on one die. Packaging technology determines bandwidth, latency and energy per bit of the connections between them.
| Approach | How dies connect | Bump pitch | Typical use |
|---|---|---|---|
| Organic substrate (2D) | Traces in a conventional package substrate | About 100-150 µm | Server and desktop CPUs with separate I/O die |
| Silicon interposer (2.5D) | Dies sit side by side on a passive silicon layer | About 40-55 µm | GPUs and accelerators with HBM |
| Embedded silicon bridge | Small silicon bridges only under die edges | About 36-55 µm | Large multi-die processors |
| 3D stacking with microbumps | Dies stacked vertically | About 25-50 µm | Cache and memory stacks |
| Hybrid bonding (3D) | Direct copper-to-copper bonding | Below 10 µm | Stacked cache, image sensors |
Finer pitch means more connections per millimeter of die edge and lower energy per bit. Short on-package links typically consume well under one picojoule per bit, far less than signals sent across a motherboard.
Die-to-die interface standards
Early chiplet products used proprietary interfaces, so only one vendor’s dies could be combined. The industry is working toward open standards so that chiplets from different suppliers can share a package.
| Interface | Type | Characteristics |
|---|---|---|
| UCIe | Open industry standard | Defines physical layer and protocols for standard and advanced packages |
| BoW (Bunch of Wires) | Open specification | Simple parallel interface for organic substrates |
| Proprietary fabrics | Vendor-specific | Tuned for one product family, not interoperable |
UCIe can carry protocols such as PCIe and CXL over the die-to-die link, which lets designers reuse familiar software and coherence models. A true open market for third-party chiplets remains at an early stage, mainly because of testing, liability and integration questions.
Chiplets compared with monolithic dies and SoCs
A chiplet design is not automatically better than a monolithic one. The comparison below shows where each approach has the advantage.
| Property | Monolithic die | Chiplet design |
|---|---|---|
| Yield at large sizes | Falls sharply with area | Higher, small dies tested individually |
| Internal latency | Lowest, all on one die | Higher across die boundaries |
| Power for internal traffic | Lowest | Extra energy for die-to-die links |
| Process flexibility | One node for everything | Different nodes per function |
| Product range from one design | Limited | Many configurations from the same dies |
| Packaging cost and complexity | Lower | Higher, advanced packaging needed |
A system on a chip (SoC) integrates CPU, GPU and other blocks on one die and remains ideal for small, power-sensitive devices such as phones. Chiplets win in large processors for servers, desktops and AI accelerators, where die size and volume variety make modularity pay off.
Limitations and design challenges
Chiplets shift complexity from the die to the package and the system design. The economic advantage appears only at sufficient die size and production volume; for small or low-volume chips, the extra packaging steps can cost more than the yield gain. Designers must also partition the architecture carefully, because every interface placed at a die boundary adds latency, power and verification effort. The main challenges are listed below.
- Latency across dies: memory or cache accesses that cross a die boundary are slower, which can affect latency-sensitive software.
- Thermal density: stacked dies trap heat, so 3D-stacked chiplets may run at lower clocks or need careful cooling.
- Power delivery: many dies with different voltages complicate the package power network.
- Test and assembly cost: advanced packaging adds process steps, and a failure after bonding can scrap several good dies.
- Software awareness: operating systems and applications benefit from topology-aware scheduling that keeps related threads on the same die.
A non-technical view
A chiplet is a small piece of a processor that is made separately and then joined with other pieces inside one package. Instead of carving one huge chip, the manufacturer builds several small ones and connects them very closely.
This is like building a house from factory-made modules instead of pouring it as one giant block. If one module is flawed, only that module is replaced. The result is cheaper, more flexible processors, at the price of a little extra delay when the pieces talk to each other.
A concrete example
A processor company wants a server CPU with 64 cores and a desktop CPU with 8 to 16 cores. A monolithic 64-core die would be very large, would suffer poor yield and would need its own design.
Instead, the company designs one 8-core compute chiplet on an advanced node and one I/O die with memory controllers and PCIe on an older, cheaper node. The server product combines eight compute chiplets with a large I/O die; the desktop product uses one or two compute chiplets with a smaller I/O die. Because all compute dies are tested before assembly, the best ones go to high-clock desktop models and the rest to servers. Two die designs serve an entire product line, and manufacturing cost per core falls substantially.