EUV lithography, short for extreme ultraviolet lithography, is the chip-patterning technique that exposes photoresist on a silicon wafer with light of 13.5 nanometer wavelength, about fourteen times shorter than the 193 nm deep ultraviolet light used before it. In semiconductors, it is the step that prints the smallest features of the most advanced logic and memory chips, and it is the main reason leading process nodes can keep shrinking transistors.
EUV is a form of photolithography, but its physics is so different that almost every part of the exposure system had to be reinvented: the light source, the optics, the mask and the resist. The result is a tool of extraordinary complexity and cost that replaces several patterning passes with a single exposure on critical layers.
How EUV lithography produces and focuses light
EUV light is produced by a laser-produced plasma source. Tiny droplets of molten tin, roughly 25 to 30 micrometers across, fall through a vacuum chamber at tens of thousands per second; a pre-pulse flattens each droplet and a powerful carbon dioxide laser then heats it into a plasma that emits at 13.5 nm. A collector mirror gathers the light and directs it into the illuminator.
Because almost every material, including air and glass, absorbs EUV strongly, the whole optical path runs in vacuum and uses mirrors instead of lenses. Each mirror is a multilayer Bragg reflector of alternating molybdenum and silicon layers, and even a perfect one reflects only about 70 percent of the light. After roughly ten reflections between source and wafer, only a small fraction of the generated power reaches the resist, which is why source power is the central engineering challenge.
The mask is also reflective, not transparent: the circuit pattern is formed by an absorber layer on top of a multilayer mirror, and the light strikes it at an angle of about 6 degrees. This oblique illumination creates mask 3D effects that designers and lithographers must correct for.
Key parameters of EUV systems
Resolution in lithography follows the Rayleigh criterion, in which the smallest printable half-pitch is proportional to the wavelength divided by the numerical aperture (NA), multiplied by a process factor k1. EUV wins mostly through the shorter wavelength, and the newer High-NA EUV systems raise the numerical aperture to improve it further.
| Parameter | Typical value | What it affects |
|---|---|---|
| Wavelength | 13.5 nm | Fundamental resolution limit |
| Numerical aperture | 0.33 standard, 0.55 High-NA | Smallest printable pitch |
| Source power | Roughly 250-600 W at intermediate focus | Wafer throughput |
| Resist dose | About 30-80 mJ per square centimeter | Throughput versus stochastic defects |
| Throughput | Order of 100-200 wafers per hour | Cost per exposed layer |
| Single-exposure pitch | Roughly 26-36 nm at 0.33 NA | Need for multiple patterning |
The figures vary with tool generation, layer type and dose, so they indicate orders of magnitude rather than guaranteed specifications. Dose is the most important trade-off: a higher dose reduces random defects but lowers the number of wafers exposed per hour.
EUV compared with deep ultraviolet lithography
Before EUV, the finest layers were printed with 193 nm immersion lithography, which places water between the lens and the wafer to raise the numerical aperture to about 1.35. To print features far below its single-exposure limit, fabs used multiple patterning, splitting one layer into two, three or four masks and exposures.
| Aspect | 193 nm immersion | EUV at 0.33 NA |
|---|---|---|
| Wavelength | 193 nm | 13.5 nm |
| Optics | Refractive lenses in water | Reflective mirrors in vacuum |
| Mask | Transmissive | Reflective multilayer |
| Critical layers | Often multiple patterning | Often single exposure |
| Process complexity | More masks and steps | Fewer steps, costlier tool |
| Main risk | Overlay errors between exposures | Stochastic defects and source uptime |
The practical benefit is simpler process flows. Replacing a multiple patterning stack with one EUV exposure removes masks, deposition and etch steps and the overlay errors between them, which can shorten cycle time and improve yield even though each EUV exposure is expensive.
Where EUV is used in chip manufacturing
EUV is applied only to the most critical layers of a chip, typically the lowest metal interconnect levels, vias and contacts, and the gate and fin cut layers. The many less demanding layers above them stay on cheaper deep ultraviolet tools, because using EUV everywhere would waste scarce and costly capacity.
| Application | Role of EUV | Reason |
|---|---|---|
| Leading logic nodes | Several to over 20 layers | Replaces multiple patterning |
| DRAM | A few critical layers | Tighter cell pitch at lower cost |
| Upper metal layers | Usually not used | 193 nm resolution is sufficient |
| High-NA EUV | Most demanding future layers | Restores single exposure at smaller pitch |
Because only a handful of semiconductor foundries and memory makers run leading nodes, the installed base of EUV scanners is concentrated, and access to EUV capacity has become a strategic factor for fabless companies choosing a manufacturing partner.
Limitations and engineering challenges
The defining limitation of EUV is photon shot noise. Each EUV photon carries about 92 electronvolts, roughly fourteen times more than a 193 nm photon, so the same dose delivers far fewer photons. Random variation in their number and absorption causes stochastic defects such as missing contacts, bridges and line-edge roughness.
- Mask defects and contamination are hard to manage because a protective pellicle must survive intense EUV light while letting most of it through.
- Resist chemistry must balance sensitivity, resolution and roughness, a trade-off often called the RLS triangle; metal-oxide resists are one response.
- High-NA optics use anamorphic magnification, which halves the exposure field and forces large chips to be stitched from two fields.
- Cost and energy use are very high, so EUV makes sense only where it simplifies the process enough to pay for itself.
The idea in brief
Chips are made by projecting a circuit pattern onto a silicon wafer, a little like exposing a photograph. The finer the light, the finer the details it can draw. EUV lithography uses extremely short-wavelength light, so it can draw lines only a few dozen atoms wide.
That light is so easily absorbed that it cannot pass through glass or even air, so the machines use mirrors inside a vacuum and create the light by hitting tiny tin droplets with a laser. The main benefit is that very small patterns can be printed in one step instead of being built up through several slower exposures.
A practical scenario
A foundry moving a mobile processor to its next logic node must print a tight-pitch metal layer. With 193 nm immersion tools, that layer would need three or four exposures with separate masks, plus extra deposition and etch steps, and each additional exposure adds overlay error.
The process team moves the layer to single EUV exposure and tunes the dose so that stochastic missing-via defects fall to an acceptable level while keeping throughput high enough. The remaining upper metal layers stay on immersion tools. The outcome is fewer process steps for that layer, a shorter wafer cycle time and better yield on the critical level, at the cost of reserving time on expensive EUV scanners.