An FPGA (field-programmable gate array) is an integrated circuit whose digital logic is defined after manufacturing by loading a configuration file, called a bitstream, into a fabric of programmable logic blocks and programmable interconnect. Among semiconductors, the FPGA sits between fixed-function chips and general-purpose processors: it executes no instruction stream by default, but becomes the circuit that the designer describes.
Because the same silicon can be reconfigured in the field, an FPGA offers hardware-level parallelism and deterministic timing without the cost and lead time of designing a custom chip. That makes it a standard choice for prototyping, low-volume products, signal processing, networking and any task that needs microsecond or nanosecond reaction times.
How an FPGA implements logic
An FPGA implements logic by combining many small configurable elements and connecting them through a programmable routing network. The basic element is the lookup table (LUT), a tiny memory with typically 4 to 6 inputs that can reproduce any Boolean function of those inputs, paired with one or more flip-flops that store state between clock edges.
LUTs and flip-flops are grouped into configurable logic blocks, and switch matrices connect these blocks horizontally and vertically. Modern devices also contain hard blocks that would be inefficient to build from LUTs: DSP slices for multiply-accumulate arithmetic, block RAM, clock managers, high-speed serial transceivers, PCIe and memory controllers, and sometimes complete processor cores.
The bitstream sets every LUT value, every routing switch and every hard-block mode. In most devices it is held in SRAM configuration cells, so it is lost at power-off and must be reloaded from external flash at every start, usually within milliseconds to a few hundred milliseconds.
| Block | Function | Typical use |
|---|---|---|
| Lookup table | Any Boolean function of 4 to 6 inputs | Control logic, state machines |
| Flip-flop | Stores one bit per clock cycle | Registers, pipelining |
| DSP slice | Hardened multiply and accumulate | Filters, FFTs, neural network inference |
| Block RAM | On-chip memory, tens of kilobits per block | Buffers, FIFOs, lookup data |
| Serial transceiver | Multi-gigabit links | Ethernet, PCIe, video interfaces |
| Clock manager | PLL or MMCM frequency synthesis | Generating and aligning clocks |
From hardware description to bitstream
FPGA design starts with a hardware description language such as VHDL or Verilog/SystemVerilog, or with high-level synthesis that converts restricted C or C++ into hardware. The code describes concurrent circuits rather than sequential steps, which is the main conceptual hurdle for software developers.
Vendor toolchains then run a fixed sequence of steps. Each step can fail or need iteration, and the slowest steps on large designs can take minutes to many hours.
- Simulation verifies behavior with testbenches before any hardware is involved.
- Synthesis translates the description into a netlist of LUTs, flip-flops and hard blocks.
- Placement and routing assign each element to a physical location and connect them.
- Static timing analysis checks that every path meets its clock constraints.
- Bitstream generation produces the configuration file loaded into the device.
Timing closure is often the hardest part. Achievable clock frequencies in typical designs range from roughly 100 to 500 MHz, far below CPU clock rates, so FPGA performance comes from parallelism and pipelining, not raw clock speed.
FPGA compared with ASIC, CPU and GPU
The FPGA occupies a middle position between flexibility and efficiency. An ASIC is a custom chip fabricated for one function on a specific process node; it is faster and far more power-efficient per operation, but it needs high non-recurring engineering costs and months of fabrication. A CPU runs any software sequentially, and a GPU runs many identical operations in parallel on fixed hardware.
| Option | Flexibility | Efficiency per task | Upfront cost | Best fit |
|---|---|---|---|---|
| FPGA | Reconfigurable hardware | High for parallel, bit-level work | Low to moderate | Low and medium volumes, deterministic latency |
| ASIC | Fixed after fabrication | Highest | Very high | Mass production |
| CPU | Any software | Low for parallel data paths | Low | General control and logic |
| GPU | Programmable kernels | High for regular floating-point math | Low | Graphics and large matrix workloads |
Many products also embed FPGA fabric inside an SoC, combining ARM processor cores with programmable logic on one die, so software handles control while the fabric handles time-critical data paths. Some teams use an FPGA as a stepping stone and later convert a stable, high-volume design into an ASIC.
Device classes and configuration memory
FPGAs differ by size, configuration technology and integrated features, and the class determines startup behavior, power and security. Capacity ranges from a few thousand logic cells in small devices to several million logic cells in the largest data center and prototyping parts.
| Configuration type | Retains configuration at power-off | Strengths | Limitations |
|---|---|---|---|
| SRAM-based | No, reloads at startup | Largest capacity, latest process nodes | External flash, bitstream exposure |
| Flash-based | Yes | Instant-on, low static power | Smaller capacity |
| Antifuse | Yes, one-time programmable | Radiation tolerance, high security | Cannot be reprogrammed |
Related programmable devices include the CPLD, which is smaller and non-volatile, and the eFPGA, an FPGA block licensed as intellectual property and embedded inside a custom chip.
When to choose an FPGA
An FPGA is the right choice when a task needs custom parallel hardware but production volumes or schedule do not justify an ASIC. The decision table below summarizes common situations.
| Situation | Recommended choice | Reason |
|---|---|---|
| Line-rate packet processing | FPGA | Deterministic latency at 10 to 400 Gb/s |
| Prototype of a future custom chip | FPGA | Run real software on the design before tape-out |
| Millions of identical units | ASIC | Lower unit cost and power |
| Mostly sequential business logic | CPU | Simpler development and maintenance |
| Training large neural networks | GPU | Mature software stack, high floating-point throughput |
Common pitfalls include underestimating development effort, since HDL design and verification take longer than equivalent software, ignoring clock domain crossings that cause rare and hard-to-reproduce faults, and leaving bitstream encryption disabled in products where the design must be protected.
Understanding it simply
Most chips are built for one job and can never change. An FPGA is different. It is a chip full of small, blank logic pieces and wires that can be connected in almost any pattern. Loading a file into the chip rewires it into a new circuit.
Think of a large box of building bricks compared with a molded plastic toy. The molded toy is cheaper and stronger if you need a million of them. The bricks let you build exactly what you need today and rebuild something else tomorrow. An FPGA is the box of bricks in chip form.
Applied in practice
A small company builds industrial camera systems that inspect bottles on a production line moving at several meters per second. Each camera streams high-resolution images, and a reject decision must arrive within a few milliseconds, which a general-purpose processor cannot guarantee under varying load.
The engineers place a mid-range FPGA with ARM cores between the image sensor and the network interface. The fabric performs demosaicing, filtering and defect detection in a pipeline that handles every pixel as it arrives, while the processor cores run configuration and reporting. When a customer later needs a new bottle shape, the team ships an updated bitstream instead of new hardware, and the existing units are upgraded in the field.