Photolithography is the semiconductor manufacturing process that transfers circuit patterns onto a silicon wafer using light. A pattern on a photomask is projected onto a light-sensitive coating called photoresist, which is then developed into a stencil that guides etching, deposition or ion implantation of the layer beneath.
In semiconductors, photolithography defines the size of every transistor, contact and wire on a chip, and it is repeated dozens of times to build the full layer stack. It is the most expensive and most precision-critical step in chip fabrication, and progress in lithography has historically set the pace of shrinking feature sizes in CPUs, GPUs, memory and SoC designs.
How photolithography patterns a wafer
Each lithography step follows a repeatable process sequence performed in a track system linked to an exposure tool called a scanner or stepper. The wafer is coated, exposed, developed and inspected before the pattern is transferred into the underlying material.
| Step | What happens | Why it matters |
|---|---|---|
| Surface preparation | Cleaning, dehydration and adhesion priming | Resist must bond uniformly |
| Resist coating | Spin-coating a thin photoresist film | Thickness controls resolution and etch resistance |
| Soft bake | Driving out solvents | Stabilizes the film before exposure |
| Alignment and exposure | Projecting the mask image onto the wafer | Sets feature size and overlay accuracy |
| Post-exposure bake | Completing chemical reactions in the resist | Sharpens the latent image |
| Development | Dissolving exposed or unexposed resist | Reveals the stencil pattern |
| Inspection and metrology | Measuring critical dimensions and overlay | Decides rework or continuation |
In a positive resist, exposed areas become soluble and wash away; in a negative resist, exposed areas harden and remain. Modern deep ultraviolet processes rely on chemically amplified resists, in which one photon releases an acid that catalyzes many reactions during the post-exposure bake.
After development, the resist pattern protects selected areas while an etch or implant step modifies the exposed material. The resist is then stripped, and the wafer moves on to the next layer, often with a different mask.
Resolution, wavelength and numerical aperture
The smallest printable feature is described by the Rayleigh criterion: resolution equals k1 times the wavelength divided by the numerical aperture (NA). Shorter wavelengths, higher NA and a lower process factor k1 all allow smaller features, and each has practical limits.
| Source | Wavelength | Typical NA | Typical use |
|---|---|---|---|
| Mercury i-line | 365 nm | Up to about 0.65 | Mature nodes, power devices, MEMS |
| KrF excimer laser | 248 nm | Up to about 0.93 | Less critical layers, older logic |
| ArF dry | 193 nm | Up to about 0.93 | Mid-range nodes |
| ArF immersion | 193 nm in water | Up to 1.35 | Critical layers with multipatterning |
| EUV | 13.5 nm | 0.33, with 0.55 high-NA tools | Most critical layers at leading nodes |
Immersion lithography places a thin film of ultrapure water between the lens and wafer, raising NA above 1.0. Extreme ultraviolet (EUV) lithography uses a tin plasma light source and reflective mirror optics in vacuum, because no lens material transmits 13.5 nm light efficiently.
Depth of focus shrinks as resolution improves, so wafer flatness, focus control and resist thickness become as critical as the optics. The k1 factor has a theoretical floor of 0.25 for single exposures, and production processes typically operate somewhat above it.
Resolution enhancement and multipatterning
When features become smaller than the wavelength, the projected image blurs. Engineers compensate with resolution enhancement techniques that modify the mask and the illumination rather than the light source.
- Optical proximity correction (OPC): deliberately distorts mask shapes so the printed result matches the design.
- Phase-shift masks: use interference to sharpen edges of dense patterns.
- Off-axis illumination: shapes the light source to improve contrast for specific pitches.
- Multipatterning: splits one dense layer into two or more exposures or uses spacer techniques such as SADP and SAQP.
Multipatterning extended 193 nm immersion lithography for several node generations, but it multiplies process steps, cost and overlay risk. EUV replaced many of these multi-exposure layers with single exposures, which simplified critical layers despite the high cost of EUV tools.
Photolithography compared with other patterning methods
Optical photolithography is the only method with the throughput required for mass production of leading-edge chips, but other techniques serve specific needs. The table compares the main alternatives.
| Method | Principle | Strength | Limitation |
|---|---|---|---|
| Optical photolithography | Projection of a mask image | Very high wafer throughput | Expensive masks and tools |
| Electron-beam lithography | Direct writing with electrons | Extremely fine features, no mask | Very slow, used for masks and research |
| Nanoimprint lithography | Mechanical stamping of resist | Fine features at lower tool cost | Defects and template wear |
| Directed self-assembly | Polymers form regular patterns | Dense periodic structures | Limited to regular layouts |
Electron-beam writers produce the photomasks themselves, so the two methods are complementary rather than competing. Mask making is a substantial part of the cost of a new chip design, especially at advanced nodes where a full mask set can be very expensive.
Process control, defects and practical limits
Lithography quality is judged by critical dimension (CD) uniformity, overlay and defect density. Overlay, the alignment of one layer to the previous layers, must be controlled to a small fraction of the feature size, typically a few nanometers at leading nodes.
| Problem | Typical cause | Consequence |
|---|---|---|
| Overlay error | Wafer distortion or stage misalignment | Shorts or opens between layers |
| CD variation | Dose, focus or resist thickness variation | Transistor speed and leakage spread |
| Stochastic defects | Photon and resist randomness at EUV | Missing or bridged contacts |
| Mask defects | Particles or pattern errors on the mask | Repeating defects on every die |
| Line edge roughness | Resist chemistry limits | Variability in small transistors |
Node names such as 3 nm or 2 nm are marketing labels rather than physical dimensions. The actual metal pitches and gate pitches are larger, and comparing processes requires looking at density and pitch data, not the name alone.
Understanding it simply
Photolithography works much like developing a photograph, but on a silicon disc. The disc is coated with a light-sensitive film, light is shone through a patterned stencil, and the film changes only where the light hits.
Washing away the changed film leaves a precise pattern that guides the next manufacturing step. Repeating this dozens of times, each with a different stencil, builds up billions of tiny switches that make up a modern chip.
Applied in practice
A chip fabrication plant producing a smartphone processor must print a critical metal layer with a pitch near the limit of 193 nm immersion tools. Using immersion alone, the layer would require self-aligned quadruple patterning, adding many deposition, etch and cleaning steps and increasing overlay risk.
The process team moves that layer to a single EUV exposure at 13.5 nm. The number of steps for the layer drops sharply and cycle time shortens, although the team must tune dose and resist to keep stochastic defects in check. Yield on the layer stabilizes after dose optimization, and the remaining less critical layers stay on cheaper immersion and KrF tools.