A process node, often called a nanometer node, is a named generation of semiconductor manufacturing technology, such as 7 nm, 5 nm or 3 nm, that defines the transistor structure, design rules and achievable density a chip foundry offers. In semiconductors, the node name tells chip designers which set of manufacturing capabilities a design will be built with, and it largely determines the chip’s performance, power consumption and cost.
The number in a node name was once a physical measurement, but today it is mainly a marketing label. A 3 nm chip contains no feature that measures 3 nanometers; the name signals that the generation offers roughly the density and efficiency improvement expected from the next step on the historical scaling curve.
What the nanometer number actually means
Until the late 1990s, the node figure matched a real dimension, roughly the gate length of the transistor or half the pitch of the densest metal lines. As scaling continued, gate lengths stopped shrinking at the same rate, and manufacturers kept naming each generation by multiplying the previous figure by about 0.7, which corresponds to doubling density on the same area.
The figures that do describe a node physically are pitches: the center-to-center distances between repeated features. Engineers compare nodes using contacted gate pitch, minimum metal pitch and the height of a standard logic cell, because these values together determine how many transistors fit into a square millimeter.
| Dimension | What it measures | Typical scale at leading nodes |
|---|---|---|
| Contacted gate pitch | Spacing between adjacent transistor gates | About 45 to 55 nm |
| Minimum metal pitch | Spacing of the densest wiring layer | About 20 to 30 nm |
| Standard cell height | Height of a basic logic cell row | Several metal pitches, often 5 to 7 tracks |
| Fin or nanosheet width | Thickness of the transistor channel | Only a few nanometers |
Because each company applies its own naming, node names are not directly comparable across foundries. A node called 10 nm at one manufacturer has historically offered density close to another manufacturer’s 7 nm. Density measured in millions of transistors per square millimeter is a fairer comparison, although it also depends on the mix of logic, memory and analog circuits.
How each new node improves a chip
A new process node is judged by its PPA gains: power, performance and area. Foundries typically quote improvement against the previous generation as either higher speed at equal power or lower power at equal speed, plus a reduction in logic area. The designer chooses which benefit to take, and cannot take the full value of all three at once.
| Metric | Typical gain per full node | Depends on |
|---|---|---|
| Speed at equal power | About 10 to 20 percent | Transistor drive current and wire resistance |
| Power at equal speed | About 20 to 35 percent | Supply voltage and leakage control |
| Logic density | About 1.5 to 1.8 times | Pitch scaling and cell architecture |
| SRAM density | Often well below logic gains | Bit-cell scaling limits |
The gains have narrowed over time. SRAM cache cells and analog circuits scale poorly, so a chip dominated by cache sees a smaller area benefit than the headline logic figure suggests. Wire resistance also rises as metal lines shrink, which limits speed improvements. This is why foundries add intermediate nodes, optimized variants of an existing node with modest gains and low migration effort.
Transistor architectures across nodes
Each era of process nodes is defined less by its number than by its transistor architecture, the physical form of the switch. Planar MOSFET transistors served until around the 28 nm and 20 nm class. Leakage at short channel lengths then forced a move to three-dimensional structures that give the gate better control of the channel.
| Architecture | Approximate node era | Key idea |
|---|---|---|
| Planar MOSFET | Down to about 20 to 28 nm | Gate sits on top of a flat channel |
| FinFET | About 16 nm to 3 nm | Gate wraps three sides of a vertical fin |
| Gate-all-around nanosheet | About 3 nm and 2 nm class onward | Gate surrounds stacked horizontal sheets |
| Complementary FET | Research and future nodes | N-type and p-type devices stacked vertically |
Alongside transistor changes, leading nodes depend on EUV lithography at 13.5 nm wavelength to print the finest layers, replacing complex multi-patterning with deep ultraviolet light. Newer generations also introduce backside power delivery, which moves power wiring beneath the transistors and frees the front-side metal layers for signals.
Process node versus related concepts
A process node is a manufacturing capability, not a product or a law, and it is often confused with neighboring ideas. Moore’s law is the observation that transistor counts double roughly every two years; process nodes are the practical steps that have delivered that trend. Photolithography is one of the manufacturing techniques a node relies on, and a semiconductor foundry is the company that offers the node to customers.
Chip designers also distinguish a node from packaging technology. A chiplet design can combine dies built on different nodes, for example compute dies on a leading node and input-output dies on an older, cheaper one. This approach has become common because not every circuit benefits from the most advanced and expensive process.
Choosing a node: cost, maturity and pitfalls
The most advanced node is not automatically the right choice. Mask sets, design tools and engineering effort grow sharply at each generation, and early defect density reduces yield, raising the cost of every good die. Mature nodes from 28 nm to 180 nm remain in heavy use for microcontrollers, power management, sensors and automotive chips.
- High-volume processors and mobile SoCs justify leading nodes because power savings and density pay back the design cost over many millions of units.
- Low-volume ASICs often fit better on mature nodes where mask costs are a fraction and design kits are stable.
- Comparing node names between foundries without checking density and pitch figures leads to wrong conclusions.
- Assuming every block shrinks equally ignores the weak scaling of SRAM, analog and input-output circuits.
The simple explanation
A process node is the generation of chip-making technology used to build a processor. Each new generation packs more tiny switches into the same space. That makes chips faster, more efficient or both.
The number in the name, such as 5 nm or 3 nm, sounds like a measurement. Today it is mostly a generation label, like a model year for cars. A smaller number means a newer and more capable process, but it does not describe the exact size of anything on the chip.
How it is used in practice
A company designing a smartphone processor must decide whether to move its next chip from a 5 nm-class node to a 3 nm-class node. The foundry’s data shows roughly 25 to 30 percent lower power at the same speed and about 1.6 times higher logic density, but cache area shrinks far less and wafer prices are noticeably higher.
The team keeps the CPU and GPU cores on the 3 nm-class node, where battery life gains matter most, and places the modem and input-output functions on a cheaper mature process in a separate die. The result is a chip with longer battery life in daily use, while total silicon cost stays within the product budget.