A silicon wafer is a thin, polished disc of monocrystalline silicon that serves as the substrate on which integrated circuits are built. In the production of semiconductors, hundreds of identical chips are patterned on one wafer at the same time, then tested and diced into individual dies. A wafer is typically 300 mm in diameter and about 775 micrometers thick in leading-edge fabs, and it is often simply called a wafer.
The wafer matters because its crystal purity, flatness and surface quality set the ceiling for every later process step. Defects measured in nanometers or contamination measured in parts per billion can lower the yield, the share of dies on a wafer that work correctly.
How a silicon wafer is made
Wafer production turns quartz-derived silicon into a near-perfect single crystal and then into flat discs. Raw metallurgical silicon is purified chemically into electronic-grade polysilicon with a purity of roughly nine to eleven nines (99.9999999% or better) before it is melted.
- Crystal growth: in the Czochralski process, a seed crystal is dipped into molten silicon at about 1,420 °C and slowly pulled while rotating, forming a cylindrical ingot up to about two meters long.
- Doping during growth: small amounts of boron (p-type) or phosphorus (n-type) are added to the melt to set the wafer’s base resistivity.
- Shaping: the ingot is ground to an exact diameter and given a notch that marks crystal orientation.
- Slicing: a multi-wire saw cuts the ingot into thin slices with minimal material loss.
- Lapping, etching and polishing: mechanical and chemical-mechanical polishing (CMP) produce a mirror surface flat to within tens of nanometers.
- Cleaning and inspection: wafers are cleaned, measured for flatness and particles, and sealed in clean carriers.
An alternative, the float-zone process, melts a narrow zone that travels along a rod without a crucible. It yields very low oxygen content and is preferred for high-power devices and detectors, but it is costlier and limited to smaller diameters.
Wafer sizes and key parameters
Wafer diameter has grown over decades because a larger wafer carries more dies per process step, which lowers cost per chip. Each transition required new equipment across the entire fab, so changes are rare and expensive. The industry explored 450 mm wafers, but that transition was shelved.
| Diameter | Typical thickness | Main use today |
|---|---|---|
| 100 mm (4 inch) | About 525 µm | Research, MEMS, compound semiconductors |
| 150 mm (6 inch) | About 675 µm | Power devices, analog, silicon carbide |
| 200 mm (8 inch) | About 725 µm | Mature nodes, sensors, microcontrollers |
| 300 mm (12 inch) | About 775 µm | Leading-edge logic, DRAM, NAND flash |
Beyond diameter, a wafer is specified by crystal orientation, dopant type and resistivity, flatness and oxygen content. Logic and memory processes usually use (100)-oriented silicon because it gives favorable transistor interface properties, while some sensors and power devices use (111).
| Parameter | Typical values | Why it matters |
|---|---|---|
| Crystal orientation | (100) or (111) | Etch behavior, carrier mobility |
| Dopant and type | Boron p-type, phosphorus n-type | Base electrical behavior of the substrate |
| Resistivity | About 1 to 100 ohm-cm for most uses | Isolation, leakage, device design |
| Site flatness | Nanometer scale across exposure fields | Lithography focus margin |
| Particle count | A handful of particles above a size limit | Defect density and yield |
From blank wafer to finished dies
Once in a semiconductor foundry, the wafer passes through hundreds to over a thousand process steps over several weeks or months. Repeated cycles of deposition, photolithography, etching, ion implantation and polishing build transistors at the bottom and many metal interconnect layers above them.
At the end, every die on the wafer is probed electrically in wafer sort, and failing dies are marked. The wafer is then thinned from the back, mounted on tape and diced with a saw or laser. Good dies go to packaging, while partial dies at the round edge are discarded, which is why edge loss is larger for very big chips.
The number of dies on a wafer depends on die area. A 300 mm wafer has about 70,000 square millimeters of area, so a 100 mm² die fits several hundred times, while a large 600 mm² processor fits fewer than a hundred. Yield falls as die size rises, because a single defect ruins a larger share of the wafer, which helps explain the move toward chiplets.
Silicon wafer compared with related substrates
A standard bulk silicon wafer is not the only substrate in semiconductor manufacturing. Engineered and compound wafers trade cost and maturity for electrical properties that bulk silicon cannot provide.
| Substrate | Key property | Typical application |
|---|---|---|
| Bulk silicon | Mature, low cost, very large diameters | Most logic, memory and microcontrollers |
| Epitaxial silicon | Grown top layer with controlled doping | CMOS image sensors, power and logic |
| Silicon on insulator (SOI) | Buried oxide reduces leakage and capacitance | RF front ends, low-power logic |
| Silicon carbide (SiC) | Wide bandgap, high voltage tolerance | Electric vehicle inverters, chargers |
| Gallium nitride on silicon | Fast switching, high electron mobility | Power adapters, RF amplifiers |
The term die names a single rectangular chip cut from the wafer, while wafer names the whole disc. Confusing the two leads to misreading yield figures, which are usually quoted per wafer but determined per die.
Defects, yield and handling risks
Because every chip inherits the wafer’s flaws, defect control is central to wafer quality. Crystal defects, metallic contamination and surface particles all reduce yield, and their impact grows as transistor features shrink toward a few nanometers.
- Crystal-originated particles and dislocations can cause leakage or gate oxide failures.
- Metal contamination such as iron or copper degrades carrier lifetime even at extremely low concentrations.
- Warp and bow disturb lithography focus and wafer chucking.
- Edge chipping from handling can propagate cracks during high-temperature steps.
- Electrostatic charge attracts particles, so wafers move in sealed FOUP carriers under robotic handling.
Fabs therefore track defect density per square centimeter and correlate inspection maps with electrical results. A recurring pattern at the same wafer location often points to a specific tool or step rather than to the incoming silicon.
In plain words
A silicon wafer is like a very large, extremely pure baking sheet for computer chips. Manufacturers grow a giant crystal of silicon, slice it into thin round discs and polish them until they are smoother than a mirror.
They then build hundreds of chips side by side on each disc, layer by layer, and finally cut the disc into separate pieces. The cleaner and flatter the wafer, the more of those chips work at the end.
A real-world example
A chipmaker producing a microcontroller for household appliances runs it on 200 mm wafers at a mature process node. The die measures about 12 mm², so each wafer holds roughly 2,000 candidate dies after edge loss is subtracted.
During a production month, wafer sort shows yields drop from about 95% to 88% on wafers from one batch. Inspection maps reveal a ring of failures near the wafer edge, and the team traces it to an edge-handling issue on one polishing tool. After the tool is adjusted, yield returns to normal, which shows how a defect on the wafer directly turns into lost chips and higher cost.